Influence of Hot Carriers and Illumination Stress on a-InGaZnO TFTs with Asymmetrical Geometry

In this study, the influence of hot carriers and illumination stress on InGaZnO thin-film-transistors (TFTs) with asymmetrical geometry was investigated by measuring the drain current-gate voltage (ID-VG) and capacitance-voltage (C-V) characteristics. Reversed ID-VG in saturated operation shows that the sub-channel effect was caused by the electric field distribution. Furthermore, COMSOL simulation of the device under stress was performed to demonstrate the abnormal degradation behavior. Upon illumination, electron-hole pairs are generated. This causes carrier trapping in the gate insulator (GI) and etch-stop-layer (ESL). Based on the weaker electric field around the U-electrode observed in the COMSOL simulation, it was concluded that uniform hole-trapping was more dominant than electron-trapping, which lowers the barrier, as can be inferred from the measured gate-to-drain (CGD) and gate-to-source capacitances (CGS).