A 4900-[Formula Omitted]m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

A 4900-[Formula Omitted]m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

1100[Formula Omitted] improvement in test vector leakage assessment (TVLA) metric in power and EM time- and frequency-domain analyses.

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Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 2020-01, Vol.55 (4), p.945
Hauptverfasser: Kumar, Raghavan, Suresh, Vikram, Kar, Monodeep, Satpathy, Sudhir, Anders, Mark A, Kaul, Himanshu, Agarwal, Amit, Hsu, Steven, Chen, Gregory K, Krishnamurthy, Ram K, De, Vivek, Mathew, Sanu K
Format: Artikel
Sprache:eng
Schlagworte:
CMOS
Frequency analysis
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Beschreibung
Zusammenfassung:1100[Formula Omitted] improvement in test vector leakage assessment (TVLA) metric in power and EM time- and frequency-domain analyses.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2960482