Line Current Ripple Minimization PWM Strategy With Reduced Zero-Sequence Circulating Current for Two Parallel Interleaved Three-Phase Converters

This article proposes a line-current ripple minimization pulsewidth modulation strategy with reduced zero-sequence circulating current (ZSCC) for two parallel three-phase two-level converters. We split each 60° sector into six subsectors, each applies the nearest three vectors to ensure minimal line-current ripple. To reduce the ZSCC, we further investigate all vector sequences of the nearest three vectors and derive an optimal vector sequence for each of the six subsectors. We unify all carrier sequences under a carrier-based modulation scheme with the assistance of voltage injections. The injected voltage can be computed by a simple algorithm that allows easy implementation in mainstream microcontrollers. The experimental results validate that the proposed method maintains the minimal line-current ripple while significantly reducing the ZSCC compared to the existing line current ripple minimization methods.