A simulation study on low voltage operability of hafnium oxide based ferroelectric FET memories

Lower limit of operable voltage for ferroelectric field effect transistor memories using hafnium oxide based ferroelectric gate dielectrics was estimated using circuit simulations. Assuming realistic array architecture, memory weakening by disturbs and restrictions set by sneak current were taken into account. For modeling ferroelectricity, a continuous Preisach model of hysteresis was used. The results show that the lowest possible operation voltage, not including variability and reliability margin, will be around ±2 V. It was found that moderate reduction of remanent polarization is beneficial for lowering both operation voltage and interfacial layer electric field stress.