Implementation of the interpolator for signal peak detection in read-out ASIC

A prototype interpolator for signal peak detection in read-out ASIC is presented. It uses interpolation algorithm for finding additional points between ADC samples. This allows to increase an accuracy for signal peak detection. Behavioral models of interpolator for Spline and Lagrange algorithm were realized and compared. Interpolator was designed in 180 nm UMC MMRF CMOS process. It is based on a 6th order Lagrange interpolation polynomial. The interpolator ensures the accuracy of signal peak finding is less than 1.5 LSB of ADC at sampling frequency of 25 MHz and 200 ns peaking time of 2nd order shaper.