Automated performance‐based design technique for an efficient LTE PDSCH implementation using SDSoC tool

Summary System on a chip (SoC) creates massive design challenges for SoC‐based designers. The design challenges start from functional, architectural verification complexity and finally meeting performance constraints. In addition, heterogeneity of components and tools introduces long design cycles. The Software‐Defined System‐on‐Chip (SDSoC) developed by Xilinx is used to create custom SoC on a heterogeneous FPGA‐CPU platform. The SDSoC tool provides fast, flexible, and short design cycle to develop heterogeneous FPGA‐CPU platform. The objective of this paper is to introduce a new automated design technique to build a SoC on a heterogeneous FPGA‐CPU platform that meets design requirements using SDSoC tool. In this paper, the typical SDSoC design flow is introduced. In addition, a new automated SDSoC design technique is developed to design SoC on a heterogeneous FPGA‐CPU platform on the basis of performance metrics such as area, power, and latency. Design of physical downlink shared channel (PDSCH) in long‐term evolution (LTE) is presented as a case study. This paper provides the implementation of the transmitter and the receiver of the PDSCH in LTE using SDSoC tool and selects a platform that meets performance metrics constraints. Automated design technique is used to implement multiples of heterogeneous FPGA‐CPU SoC platforms using SDSoC tool. This paper answers the questions of what platform and what implementation, whetherhardware or software is best suited for more efficient platform. Also, this paper answers the questions of what SoC platform to be implemented for best overall performance by introducing Figure of Merit (FoM) metric. Quantum leap in the design of heterogeneous FPGA‐CPU SoC platform by integrating performance design constraint requirement in the design cycle.