FPGA‐based implementation of single‐phase seven‐level quasi‐Z‐source inverter
Summary In this paper, a new single‐phase seven‐level quasi‐Z‐source (qZs) inverter with reduced switch count for multistring photovoltaic applications is proposed, which is capable of supplying both direct current (dc) and alternating current (ac) loads simultaneously. The proposed configuration is...
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Veröffentlicht in: | International journal of circuit theory and applications 2019-12, Vol.47 (12), p.1970-1989 |
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Format: | Artikel |
Sprache: | eng |
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In this paper, a new single‐phase seven‐level quasi‐Z‐source (qZs) inverter with reduced switch count for multistring photovoltaic applications is proposed, which is capable of supplying both direct current (dc) and alternating current (ac) loads simultaneously. The proposed configuration is derived from a combination of qZs networks and asymmetrical seven‐level inverter. The front‐end qZs converter boosts the input voltage obtained from the dc sources to the desired value, whereas the asymmetrical seven‐level inverter performs dc‐ac conversion with reduced switch count and provides better efficiency. The steady‐state performance of the model is evaluated in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of operation. In addition, the dynamic performance of the model is tested for the load as well as input voltage changes. A simple proportional‐integral (PI) controller is implemented in FPGA Spartan‐6 Processor using Xilinx system generator blocks. An experimental prototype is also developed to validate the feasibility of the proposed topology. Finally, a brief comparative assessment is formulated with other topologies to show the merits of the proposed structure.
A new structure of quasi‐Z‐source–based MLI is proposed for multistring PV applications. The proposed topology has the merits of reduced switch count, simple control, modularity, and high efficiency. The performance of the model is evaluated in CCM and DCM modes for different loads under steady state. The dynamic response of the system is verified through simulation and a prototype model using Xilinx FPGA‐based control signals in a real‐time environment. |
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ISSN: | 0098-9886 1097-007X |
DOI: | 10.1002/cta.2709 |