Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems

The hardware footprint for S-box specification in lightweight block cipher as appropriate to IoT and CPS information security systems is presented in this paper. The S-box Boolean function in the lightweight block cipher is defined using the Reed-Muller structure. A Rule Based–Common Sub-structure S...

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Veröffentlicht in:Integration (Amsterdam) 2019-11, Vol.69, p.266-278
Hauptverfasser: Prathiba, A., Kanchana Bhaaskaran, V.S.
Format: Artikel
Sprache:eng
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Zusammenfassung:The hardware footprint for S-box specification in lightweight block cipher as appropriate to IoT and CPS information security systems is presented in this paper. The S-box Boolean function in the lightweight block cipher is defined using the Reed-Muller structure. A Rule Based–Common Sub-structure Sharing Optimization (RB-CSSO) algorithm has been proposed towards improving the performance efficiency of Reed-Muller structure. This novel hybrid RB-CSSO optimization mechanism first transforms the direct Positive Polarity Reed Muller (PPRM) S-box representation into Mixed Polarity Reed-Muller (MPRM) S-box architecture using local rule based transformation. Secondly, the Common Sub Term (CST) and Common Sub-expression (CSE) merging/elimination are employed over the resulting MPRM structure. The combined rule-based transformation and the common sub-function sharing demonstrate an overall reduction in area, delay and power of the Reed-Muller S-box structure. Both the theoretical analysis and the experimental verification demonstrate reduction in area and delay of S-box. Post synthesis results based on ASIC standard cell based implementations have been used to analyze area, delay and power values across Process, Voltage and Temperature (PVT) corners for a wide range of operating conditions. Extensive comparisons between direct PPRM and optimized MPRM implementations have been carried out. The post layout simulations of S-box structures realized show the advantages of lower area-delay product, power-area product and power-delay product. This work thus authenticates the application of proposed structure for lightweight, resource constrained security systems. Industry standard full suite of Cadence® tools have been employed in the simulations using 65 nm TCBN65GPLUS standard cells of TSMC technology library. •Lightweight Cryptography; symmetric block ciphers; Substitution box; Reed-Muller structure, hardware architecture.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2019.05.003