Adaptive Transport in High Performance ( I on), Steep Sub-Threshold Slope (SS < 60 mV/dec) MoS2 Transistors

We demonstrate a rendition of an ‘ideal’ low power transistor, by combining the advantages of a tunnel FET (steep subthreshold slope (SS < 60 mV/dec)) with that of a thermionic FET (high ON current) in the same device. A dual-gated multilayer MoS2 FET is fabricated keeping in view independent gate control and careful deliberation of device architecture and materials processing. This device is capable of operating in two distinct regimes (i) A low power tunnelling regime with steep SS and operational voltages < 0.5 V OR (ii) A high mobility and I on, thermionic regime. Second, an intuitive modification in the device structure can dynamically tune the threshold voltage [Formula Omitted] and transport from OFF (tunnelling) to ON (thermionic) state, yielding the dual benefits of tunnelling and thermionic transport in the same operational cycle. The devices demonstrate hysteresis-free, steep SS (SSmin 3.4 mV/dec and SSavg 29.3 mV/dec for 3 dec) and high mobility/ I on (100 cm2V−1s−1/0.16 μ A μ m−1) at an ultra-scaled V ds of 10 mV. To gather further insight into the transport mechanism of these devices, temperature dependent analysis of SS and I on is presented, and explained using a simple semi-classical model.