A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip

A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip

A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential sign...

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Veröffentlicht in:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Communications and Computer Sciences, 2019/06/01, Vol.E102.A(6), pp.783-787
Hauptverfasser: LEE, Pil-Ho, JANG, Young-Chan
Format: Artikel
Sprache:eng
Schlagworte:
Buffers
Field programmable gate arrays
FPGA-based frame generator
Low voltage
LVDS
Microprocessors
MIPI D-PHY
Signaling
SLVS
transmission buffer chip
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Zusammenfassung:A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.
ISSN:0916-8508
1745-1337
DOI:10.1587/transfun.E102.A.783