A PC knowledge-based environment for VLSI layout verification

This article presents an integrated rule-based environment for VLSI layout verification. This environment comprises a user interface, a rule base, an inference mechanism consisting of a hierarchical design-rule checker (DRC) and a circuit extractor (EXT), and a general purpose graphics system. This environment is called CULANS Cairo University Layout ANalysi S. The inference mechanism, denoted by DRC-EXT, uses a pattern recognition approach to perform design-rule checking and circuit extraction simultaneously. It interprets the rules of the knowledge base and the data of the input layout in terms of rectangular interaction patters. Consequently, it searches the layout to discover design-rule violations or to recognize the circuit elements. To avoid the combinatorial explosion, a heuristic search is used so that the search space is considerably reduced. The implemented heuristic search exploits a branch and bound technique that has been augmented in a dynamic programming scheme. To accomplish efficient design-rule checking and circuit extraction, CULANS utilizes the internal hierarchy of the VLSI circuit to an arbitrary number of hierarchical levels.