A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems

This paper presents a CMOS DSRC transmitter architecture for China electronic toll collection systems. A digitally configurable transmitter architecture is proposed to reduce chip area, power, cost, and design complexity. This transmitter consists of only two digitally configurable analog blocks: an ASK modulator and a power amplifier, other than the digital baseband. The use of digital configuration extends output dynamic range, and facilitates rapid prototyping in different process technologies. The RF-SoC is fabricated using a 0.13 μm CMOS technology. Chip measurement results show that the maximum output power from a single-end port is 7.23 dBm, the occupied bandwidth is 2 MHz, the adjacent channel power ratio is −38 dBc at a 10 MHz offset, the adjustment range of modulation index is 77%–95%, and the transmitter dissipates 36 mA in active mode under a 2 V supply. Compared with state-of-the-art designs in the literature, this design demonstrates remarkable advantages in design complexity, modulation index, chip area, power consumption, output dynamic range, and output peak power. The chip area savings is at least 60%, the power consumption is reduced by at least 10%, the output dynamic range is enhanced by 9%, and the single-end output peak power is improved by at least 45%. •This paper presents a CMOS DSRC transmitter architecture for China electronic toll collection systems.•A digitally configurable transmitter architecture is proposed to reduce chip area, power, cost, and design complexity.•The use of digital configuration extends output dynamic range, and facilitates rapid prototyping in different technologies.•The RF-SoC is fabricated using a 0.13 μm CMOS technology.•Chip measurement shows remarkable advantages in chip area, power consumption, output dynamic range, and output peak power.