Design and implementation of a digital down/up conversion directly from/to RF channels in HDL
The paper presents the design and implementation of a Digital Down Converter (DDC) and a Digital Up Converter (DUC) directly from/to RF channels. The project uses multi-stage decimation and interpolation by means of recursive Cascaded Integrator-Comb (CIC) filters and polyphase filters in HDL. The d...
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Veröffentlicht in: | Integration (Amsterdam) 2019-09, Vol.68, p.30-37 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | The paper presents the design and implementation of a Digital Down Converter (DDC) and a Digital Up Converter (DUC) directly from/to RF channels. The project uses multi-stage decimation and interpolation by means of recursive Cascaded Integrator-Comb (CIC) filters and polyphase filters in HDL. The design incorporates a Spectral Emission Mask (SEM) for the Internet of Things (IoT) IEEE 802.11ah Wi-Fi HaLow standard. Although the designs were implemented for 16 MHz-bandwidth in the 900 MHz frequency band, they are flexible and they can be easily adapted for other communications systems. The converter designs use HDL Coder for several fixed-point word-length representation of coefficients presenting its impact on performance. In the simulations, the DDC/DUC frequency responses were evaluated using high-level models showing that the equivalent filter design meets the requirements of the spectral mask by an appropriated representation of the fixed-point data types. The paper also shows a reformulation of the internal fixed-point data types used at the filter structures.
•Design of digital down/up converter directly from/to RF channels.•Complete DDC and DUC design equations and technical concepts.•DDC and DUC FPGA implementation with spectral emission mask.•CIC and polyphase filter implementation well-adapted to FPGA/VLSI designs.•The designs are flexible and can be easily adapted to other communications systems. |
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ISSN: | 0167-9260 1872-7522 |
DOI: | 10.1016/j.vlsi.2019.05.006 |