A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-[Formula Omitted]s Settling Time for Multi-ISM-Band ULP Radios
This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively shorten the calibration time, while the split...
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Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-01, Vol.66 (9), p.3307 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively shorten the calibration time, while the split coarse-fine PLL loops with different loop bandwidths accelerate the loop settling speed. The employed ring VCO (RVCO) aids to extend the frequency tuning range and generate multi-phase outputs. Prototyped in 65-nm CMOS, the DPLL consumes 1.2–2.4 mW over a wide frequency locking range of 68.3% (1.3–2.65 GHz) and occupies a die area of 0.12 mm2. The settling time measures [Formula Omitted] at an 82-MHz initial frequency error. |
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ISSN: | 1549-8328 1558-0806 |
DOI: | 10.1109/TCSI.2019.2926512 |