A Ternary Decision Diagram (TDD)-Based Synthesis Approach for Ternary Logic Circuits

Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multi-polarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.