A Fully Integrated 384-Element, 16-Tile, [Formula Omitted]-Band Phased Array With Self-Alignment and Self-Test
This paper describes the design and implementation of a scalable [Formula Omitted]-band phased-array system, with built-in self-alignment and self-test, based on an RFIC transceiver chipset manufactured in the TowerJazz 0.18-[Formula Omitted] SiGe BiCMOS technology with [Formula Omitted] of 240/270...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2019-01, Vol.54 (9), p.2419 |
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Sprache: | eng |
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Zusammenfassung: | This paper describes the design and implementation of a scalable [Formula Omitted]-band phased-array system, with built-in self-alignment and self-test, based on an RFIC transceiver chipset manufactured in the TowerJazz 0.18-[Formula Omitted] SiGe BiCMOS technology with [Formula Omitted] of 240/270 GHz. The RFIC integrates 24 phase-shifter elements (16TX/8RX or 8TX/16RX) as well as direct up- and down-converters, phase-locked loop with prime-ratio frequency multiplier, analog baseband, beam lookup memory, and diagnostic circuits for performance monitoring. Two organic printed circuit board (PCB) interposers with integrated antenna sub-arrays are designed and co-assembled with the RFIC chipsets to produce a scalable phased-array tile. Tiles are phase-aligned to one another through a daisy-chained local oscillator (LO) synchronization signal. Statistical analysis of the effects of LO misalignment between tiles on beam patterns is presented. Sixteen tiles are combined onto a carrier PCB to create a 384-element (256TX/128RX) phased-array system. A maximum saturated effective isotropic radiated power (EIRP) of 60 dBm (1 kW) is measured at boresight for the 256 transmit elements. Wireless links operating at 90.7 GHz using a 16-QAM constellation at a reduced EIRP of 52 dBm produced data rates beyond 10 Gb/s for an equivalent link distance in excess of 250 m. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2019.2928694 |