Single-Chip 3072-Element-Channel Transceiver/128-Subarray-Channel 2-D Array IC With Analog RX and All-Digital TX Beamformer for Echocardiography

This paper presents a single-chip 3072-element-channel (ECh) transceiver/128-subarray-channel (SCh) 2-D array IC with analog receiver (RX) and all-digital transmitter (TX) beamformer for echocardiography. The proposed IC integrates 3072-ECh transceivers that are composed of a low-power tunable ampli...

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Veröffentlicht in:IEEE journal of solid-state circuits 2019-09, Vol.54 (9), p.2555-2567
Hauptverfasser: Igarashi, Yutaka, Kajiyama, Shinya, Katsube, Yusaku, Nishimoto, Takuma, Nakagawa, Tatsuo, Okuma, Yasuyuki, Nakamura, Yohei, Terada, Takahide, Yamawaki, Taizo, Yazaki, Toru, Hayashi, Yoshihiro, Amino, Kazuhiro, Kaneko, Takuya, Tanaka, Hiroki
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Sprache:eng
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Zusammenfassung:This paper presents a single-chip 3072-element-channel (ECh) transceiver/128-subarray-channel (SCh) 2-D array IC with analog receiver (RX) and all-digital transmitter (TX) beamformer for echocardiography. The proposed IC integrates 3072-ECh transceivers that are composed of a low-power tunable amplitude three-level pulser (TA3LP), zero-power-TX-and-RX- isolation switch (ZTRSW), programmable gain-and-input-impedance low-noise amplifier (PGZLNA), bidirectional dynamically reconfigurable switched-capacitor delayer (BDR- SCD), and 24-ECh-to-1-SCh charge-domain adder (CDADD). It also has 128-SCh low-noise cable buffers (LNCBUFs) and all the related peripheral circuits, including control and interface circuits. It has an all-digital TX architecture with a digital beamformer (TX-DBF) that is free from the waveform distortion and timing error caused by long cable propagation between the main instrument unit and the IC. The TA3LP launches the three-level bipolar signals that are necessary for tissue harmonic imaging (THI). The BDR-SCD can delay 2-bit TX digital signals or an RX analog signal; 24 RX signals in an SCh are coherently delayed using BDR-SCDs, summed in the charge domain with a CDADD without signal headroom concerns, and converted into an SCh signal. The proposed IC is fabricated with a 0.18-\mu \text{m} high-voltage silicon-on-insulator (HV SOI) CMOS process. Each ECh transceiver occupies only a 300 ~\mu \text{m}\,\,\times 300 ~\mu \text{m} silicon area while having a greater than 85-dB dynamic range, 25-ns resolution, 750-ns maximum time delay, and 138-{V}_{\textrm {pp}} output capabilities. The total die size is 417 mm 2 . An ultrasound system was also made to visualize 2-D/3-D phantom images with 0.74-mW/ECh power consumption in the B-mode.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2921697