Simulation Study of Overlap Capacitance in Source-Gated Transistors for Current-Mode Pixel Drivers

Simulation Study of Overlap Capacitance in Source-Gated Transistors for Current-Mode Pixel Drivers

Contrary to conventional design principles, current-driven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5-10- \mu \text{m} gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE electron device letters 2019-09, Vol.40 (9), p.1451-1454
Hauptverfasser: Drury, Raymond, Bestelink, Eva, Sporea, Radu A.
Format: Artikel
Sprache:eng
Schlagworte:
active matrix
Capacitance
Capacitors
Circuits
Computer simulation
display
energy efficiency
Fabrication
High gain
layout optimization
Logic gates
OLED
Organic light emitting diodes
pixel circuit
Pixels
Robustness (mathematics)
Schottky barrier
Semiconductor devices
Sensor arrays
TFT
Thin film transistors
Transistors
Viability
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Contrary to conventional design principles, current-driven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5-10- \mu \text{m} gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be compensated by reducing the pixel storage capacitor. The numerical simulations demonstrate the viability of SGTs for emissive pixel drivers and high gain, low power, and robust circuits for emerging sensor arrays.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2019.2926351