Fabrication and Characterization of 3.3-kV SiC DMOSFET with Self-Aligned Channels Formed by Tilted Ion Implantation

Fabrication and Characterization of 3.3-kV SiC DMOSFET with Self-Aligned Channels Formed by Tilted Ion Implantation

SiC DMOSFET with self-aligned channels was fabricated and characterized. The process features self-aligned channel formation by utilizing tilted ion implantation. We confirmed that channel areas were successfully formed along both sides of the stripe cell. Electrical measurements revealed that the c...

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Veröffentlicht in:Materials science forum 2019-07, Vol.963, p.390-393
Hauptverfasser: Morikawa, Takahiro, Sato, Shintaroh, Shima, Akio
Format: Artikel
Sprache:eng
Schlagworte:
Alignment
Channels
Chip formation
Electrical measurement
Ion implantation
Self alignment
Silicon carbide
Threshold voltage
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Zusammenfassung:SiC DMOSFET with self-aligned channels was fabricated and characterized. The process features self-aligned channel formation by utilizing tilted ion implantation. We confirmed that channel areas were successfully formed along both sides of the stripe cell. Electrical measurements revealed that the characteristics of the fabricated DMOSFET chips had sufficiently high blocking voltage and moderate values of threshold voltage and on-state resistance. These experimental results show the proposed process can be an easy option for fabrication of SiC DMOSFET.
ISSN:0255-5476
1662-9752
1662-9752
DOI:10.4028/www.scientific.net/MSF.963.390