Circuit power optimization using pipelining and dual-supply voltage assignment
Power is one of the most important metrics in the modern integrated circuit design. We optimize the circuit power using two major approaches, pipelining and dual-supply voltage (dual-Vdd) assignment. To improve power efficiency, we have designed a new pipelining to reduce the number of gates need to...
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| Veröffentlicht in: | Integration (Amsterdam) 2019-03, Vol.65, p.241-251 |
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| creator | Xu, Teng Potkonjak, Miodrag |
| description | Power is one of the most important metrics in the modern integrated circuit design. We optimize the circuit power using two major approaches, pipelining and dual-supply voltage (dual-Vdd) assignment. To improve power efficiency, we have designed a new pipelining to reduce the number of gates need to be assigned to the high supply voltage when combined with the dual-Vdd assignment. Our overall design is tested on a set of standard ISCAS-85 benchmark circuits using an industrial cell library. An average power saving of more than 10% under a specified target delay is observed.
•A novel pipeline design customized for dual supply voltage assignment is proposed.•Our pipelining minimize the gates on high supply voltage to reduce circuit power.•An optimized dual-supply voltage algorithm on pipelined circuit is proposed. |
| doi_str_mv | 10.1016/j.vlsi.2017.12.011 |
| format | Article |
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•A novel pipeline design customized for dual supply voltage assignment is proposed.•Our pipelining minimize the gates on high supply voltage to reduce circuit power.•An optimized dual-supply voltage algorithm on pipelined circuit is proposed.</description><subject>Circuit design</subject><subject>Circuit optimization</subject><subject>Circuits</subject><subject>Design</subject><subject>Design optimization</subject><subject>Dual-supply voltage</subject><subject>Electric potential</subject><subject>Energy conservation</subject><subject>Gates (circuits)</subject><subject>Integrated circuits</subject><subject>Low power design</subject><subject>Optimization</subject><subject>Pipelines</subject><subject>Power efficiency</subject><subject>Power modeling</subject><subject>Power supply</subject><subject>Studies</subject><issn>0167-9260</issn><issn>1872-7522</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><recordid>eNp9kLFOwzAQhi0EEqXwAkyRmBN8ThMnEguqoCBVsMBsOc6lcpTaxnaKytOTqMxMd8P_3f36CLkFmgGF8r7PDkPQGaPAM2AZBTgjC6g4S3nB2DlZTCGe1qykl-QqhJ5SCiteLMjbWns16pg4-40-sS7qvf6RUVuTjEGbXeK0w0GbeZWmTdpRDmkYnRuOycEOUe4wkSHondmjidfkopNDwJu_uSSfz08f65d0-755XT9uU8V4HadSsuCgZFdJaLqCt0Wdt5gr3qiyRiiqulGrBkEyQNms6hIaRrtaQVO2ijKeL8nd6a7z9mvEEEVvR2-ml4KxooQ8zyuYUuyUUt6G4LETzuu99EcBVMzeRC9mb2L2JoCJydsEPZwgnPofNHoRlEajsNUeVRSt1f_hv6ePeGA</recordid><startdate>201903</startdate><enddate>201903</enddate><creator>Xu, Teng</creator><creator>Potkonjak, Miodrag</creator><general>Elsevier B.V</general><general>Elsevier BV</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>201903</creationdate><title>Circuit power optimization using pipelining and dual-supply voltage assignment</title><author>Xu, Teng ; Potkonjak, Miodrag</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c279t-75a571caf8a1bf57d593de3c7bc69e1589bc4be1a21eab4961b20f9c1b6dc0273</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Circuit design</topic><topic>Circuit optimization</topic><topic>Circuits</topic><topic>Design</topic><topic>Design optimization</topic><topic>Dual-supply voltage</topic><topic>Electric potential</topic><topic>Energy conservation</topic><topic>Gates (circuits)</topic><topic>Integrated circuits</topic><topic>Low power design</topic><topic>Optimization</topic><topic>Pipelines</topic><topic>Power efficiency</topic><topic>Power modeling</topic><topic>Power supply</topic><topic>Studies</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xu, Teng</creatorcontrib><creatorcontrib>Potkonjak, Miodrag</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integration (Amsterdam)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Xu, Teng</au><au>Potkonjak, Miodrag</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Circuit power optimization using pipelining and dual-supply voltage assignment</atitle><jtitle>Integration (Amsterdam)</jtitle><date>2019-03</date><risdate>2019</risdate><volume>65</volume><spage>241</spage><epage>251</epage><pages>241-251</pages><issn>0167-9260</issn><eissn>1872-7522</eissn><abstract>Power is one of the most important metrics in the modern integrated circuit design. We optimize the circuit power using two major approaches, pipelining and dual-supply voltage (dual-Vdd) assignment. To improve power efficiency, we have designed a new pipelining to reduce the number of gates need to be assigned to the high supply voltage when combined with the dual-Vdd assignment. Our overall design is tested on a set of standard ISCAS-85 benchmark circuits using an industrial cell library. An average power saving of more than 10% under a specified target delay is observed.
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| ispartof | Integration (Amsterdam), 2019-03, Vol.65, p.241-251 |
| issn | 0167-9260 1872-7522 |
| language | eng |
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| source | Access via ScienceDirect (Elsevier) |
| subjects | Circuit design Circuit optimization Circuits Design Design optimization Dual-supply voltage Electric potential Energy conservation Gates (circuits) Integrated circuits Low power design Optimization Pipelines Power efficiency Power modeling Power supply Studies |
| title | Circuit power optimization using pipelining and dual-supply voltage assignment |
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