Circuit power optimization using pipelining and dual-supply voltage assignment

Power is one of the most important metrics in the modern integrated circuit design. We optimize the circuit power using two major approaches, pipelining and dual-supply voltage (dual-Vdd) assignment. To improve power efficiency, we have designed a new pipelining to reduce the number of gates need to be assigned to the high supply voltage when combined with the dual-Vdd assignment. Our overall design is tested on a set of standard ISCAS-85 benchmark circuits using an industrial cell library. An average power saving of more than 10% under a specified target delay is observed. •A novel pipeline design customized for dual supply voltage assignment is proposed.•Our pipelining minimize the gates on high supply voltage to reduce circuit power.•An optimized dual-supply voltage algorithm on pipelined circuit is proposed.