Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications

This paper presents a novel low-complexity multi-mode multi-way split-row (split by factors of 2, 4, and 8) partially parallel pipelined layered low-density parity-check (LDPC) decoder architecture that is suitable for gigabit wireless communications. The innovative feature of the proposed decoder is related to the multi-way split-row layered LDPC decoding algorithm and architecture design techniques. Furthermore, we employed an efficient parity-check matrix-reordering method that uses row reordering, column reordering, and a local switching network to develop a multi-mode decoder that can support all four code rates specified in the IEEE 802.11ad standard. The proposed decoder can effectively reduce the complexity by a factor that is equal to the splitting factor, while the effect on the overall error-performance loss is negligible. Post-synthesis implementation results on TSMC 40-nm CMOS technology show that the proposed approach achieves higher area efficiency (throughput-to-area ratio) compared with other related previous works. For all four code rates, the proposed split-row pipelined layered LDPC decoder architecture (s = 2) occupies an area of 0.168 mm2 and achieves an encoded throughput of 11.8 Gb/s at five decoding iterations. •A novel multi-mode multi-way split-row partially parallel pipelined layered QC-LDPC decoder architecture is presented.•A multi-way split-row layered LDPC decoding algorithm is proposed.•An efficient parity-check matrix-reordering method is presented.•The proposed QC-LDPC decoder can effectively reduce the complexity by a factor that is equal to the splitting factor s.•Proposed LDPC decoder (s = 2) occupies an area of 0.168 mm2 and achieves a throughput of 11.8 Gb/s at 5 decoding iterations.•The proposed approach achieves the highest area efficiency compared with other related previous works.