Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons

Because of fabrication compatibility to current semiconductor technology, three-dimensional integrated circuits (3D-ICs) offer promising near-term solutions for maintaining Moore’s Law. 3D-ICs proffer high system speeds, massively parallel processing, low power consumption, and their high densities...

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Veröffentlicht in:Integration (Amsterdam) 2019-03, Vol.65, p.273-281
Hauptverfasser: An, Hongyu, Ehsan, M. Amimul, Zhou, Zhen, Shen, Fangyang, Yi, Yang
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Sprache:eng
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Zusammenfassung:Because of fabrication compatibility to current semiconductor technology, three-dimensional integrated circuits (3D-ICs) offer promising near-term solutions for maintaining Moore’s Law. 3D-ICs proffer high system speeds, massively parallel processing, low power consumption, and their high densities result in small footprints. In this paper, a novel 3D neuromorphic IC architecture which combines monolithic 3D integration and a synaptic array based on vertical resistive random-access memory structure (V-RRAM) is proposed. To analyze the electrical characteristics of the proposed synaptic array, a concise equivalent circuit model of the system is developed, and analytical calculations for each parameter of the equivalent circuit are provided. Moreover, a novel signal intensity encoding neuron design that can directly convert analog signal into a spiking waveform sequence is proposed and analyzed. A feasible 3D neuromorphic computing architecture is demonstrated. Applying the monolithic 3D integration technology on neuromorphic computing system hardware implementation can reduce the power consumption by 50%, and shrink die areas by 35%. •A three-dimensional Neuromorphic Computing System combing nanoscale device memristor and CMOS based neuron is proposed.•A novel Signal Intensity Encoding Neuron is proposed, which transforms input signal intensity to firing rate directly.•The design area and power consumption of the proposed system are reduced significantly compared to CMOS based design.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2017.10.009