HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations

[...]for FPGA a different case is expected due to the unpredictable placement and routing compared to ASIC, especially for large size transforms. [...]the present paper provides experimental results on comparing energy efficiency for small (4x4 and 8x8) and large size (16x16) transforms for FPGA and ASIC implementations. The state diagram also can be reused for the larger size by change the value of N, it depends on the TU size. 4.Results and Analysis The 2D-DCT architecture for 4x4, 8x8 and 16x16 TU size has been designed using Verilog HDL and implemented in Silterra 180nm technology process for ASIC and Xilinx Kintex Ultrascale for FPGA. [...]in terms of throughput, parallel architectures have higher throughput compared to the folded architecture. Because of this, the folded architecture generally results in better energy efficiency in FPGAs. 5.Conclusion In this paper, a comparison study has been performed for 2-D HEVC DCT for ASIC and FPGA implementations.