Low‐loss 7‐bit S‐band CMOS passive phase shifter with digital control

Summary This paper presents the design and implementation of a 7‐bit S‐band digital passive phase shifter using Complementary Metal‐Oxide‐Semiconductor (CMOS) 65‐nm technology in 2.6‐ to 3.2‐GHz frequency band. New switched delay network topology has been used for 5.625° and 2.8°, and modified switched filter topology has been used for implementation of other phase bits to achieve 7‐bit performance with low insertion loss and better isolation. The measured results of the fabricated chip show 7‐bit performance with an average insertion loss of 11 dB, average root mean square (RMS) phase error of less than 2.0°, average RMS amplitude error of less than 0.6 dB, input matching (S11) better than −7.5 dB, and output matching (S22) better than −14.5 dB across the target frequency band at 50Ω input/output impedance. This paper presents the design and implementation of a 7‐bit S‐band digital passive phase shifter using CMOS 65‐nm technology in 2.6‐ to 3.2‐GHz frequency band. New switched delay network topology has been used for 5.625° and 2.8°, and modified switched filter topology has been used for implementation of other phase bits to achieve 7‐bit performance with low insertion loss and better isolation. Measured results of the fabricated chip show 7‐bit performance with an average insertion loss of 11 dB, RMS phase error of less than 2°, RMS amplitude error of less than 0.5 dB, input matching greater than −7.5 dB, and output matching greater than−14.5 dB across the target frequency band.