Performance of reconfigurable architectures for image-processing applications

Reconfigurable architectures combine a programmable–visible interface and the high-level aspects of a computer’s design. The goal of this work is to explore the architectural behaviour of remote reconfigurable systems that are part of general-purpose computers. Our approach analyses various issues arising from the connection of processors with FPGA-based microarchitecture to an existing commodity microprocessor via a standard bus. The quantitative evaluation considers image-processing applications and shows that the maximum performance depends on the amount of data processed by the reconfigurable hardware. Taking images with 256 × 256 pixels, a moderate FPGA capacity of 1E+5 logic blocks provides two orders of magnitude of performance improvement over a Pentium III processor for most of our benchmarks. However, the performance benefits exhibited by reconfigurable architectures may be deeply influenced by some design parameters. This paper studies the impact of hardware capacity, reconfiguration time, memory organisation, and bus bandwidth on the performance achieved by FPGA-based systems. Those image-processing benchmarks that can exhibit high-performance improvement would require about 150 memory banks of 256 bytes each and a bus bandwidth as high as 30 GB/s. This quantitative approach can be applied to the design of high-performance reconfigurable coprocessors for multimedia applications.