Timing Characterization for RSFQ Cell Library

As superconducting circuits grow in complexity, full transient simulation and verification at the Josephson junction level using analog circuit simulators become increasingly computationally expensive. To enable faster functional and timing verification using timing back annotation and static timing analysis, logic models of rapid single flux quantum library cells are developed using hardware description languages like Verilog together with the required timing characteristics. These include propagation delays and minimum pin-to-pin pulse arrival time separation at various process and operating corners. These timing parameters must satisfy required margins and yield using Monte Carlo simulations with statistical variations. For each library cell, these timing parameters depend not only on the adjacent cells but also on their internal states. These delay variations are driven by bias current redistribution, load inductance, and load junction critical currents. We present our methodology for extracting these timing parameters to enable timing back annotation and static timing analysis. We demonstrate our methodology with a parallel counter as a reference circuit and show that timing back annotated simulation can closely match results from full circuit simulation.