Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

Miniaturization of semiconductor industries paved the way for rapid development in the field of digital electronics. In DSM range, power dissipation has become a major concern due to leakage currents; hence, researchers are continuously trying to evolve ways to mitigate this. Out of many such ways the use of carbon nanotube technology is a promising way to design low-power circuits, as carbon has a property of providing variable threshold voltage ( V TH ) in N-type transistors. Here simulation results confirm that CNTFET has better performance than MOS and FinFET technologies in low-power world. In this paper existing and proposed adiabatic logic is implemented by CNTFET technology at 32 nm in HSPICE by using Predictive Technology Model (PTM). Comparison of simulation results shows that proposed CNTFET-based ON–OFF-DCDB-PFAL adiabatic logic saves average power 94.33% in Buffer/NOT, 93.13% in NAND/AND, 93.14% in NOR/OR, 91.76% in XOR/XNOR when compared with 2N2N2P circuit at 10 MHz frequency.