Zero-Ripple Input-Current High-Step-Up Boost–SEPIC DC–DC Converter With Reduced Switch-Voltage Stress
This paper proposes a zero-ripple input-current high-step-up boost-single ended primary inductor converter (SEPIC) dc-dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost-SEPIC dc-dc converter. In the proposed converter, the input current ripp...
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| Veröffentlicht in: | IEEE transactions on power electronics 2017-08, Vol.32 (8), p.6170-6177 |
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| container_title | IEEE transactions on power electronics |
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| creator | Lee, Sin-Woo Do, Hyun-Lark |
| description | This paper proposes a zero-ripple input-current high-step-up boost-single ended primary inductor converter (SEPIC) dc-dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost-SEPIC dc-dc converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low R ds(on) , can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype. |
| doi_str_mv | 10.1109/TPEL.2016.2615303 |
| format | Article |
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In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low R ds(on) , can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype.</description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2016.2615303</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Capacitors ; Cascaded boost–single ended primary inductor converter (SEPIC) converter ; Circuits ; Clamping circuits ; Clamps ; Converters ; DC-DC power converters ; Electric potential ; Energy conversion efficiency ; high-step-up converter ; Inductors ; MOSFETs ; Power efficiency ; ripple-free technic ; Stress ; Switches ; Switching circuits ; Voltage converters (DC to DC) ; Voltage gain</subject><ispartof>IEEE transactions on power electronics, 2017-08, Vol.32 (8), p.6170-6177</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-1ace35d642869edbf45a29fe5c48569b5d44fc0341b322f86e5d44bb3f87ac143</citedby><cites>FETCH-LOGICAL-c293t-1ace35d642869edbf45a29fe5c48569b5d44fc0341b322f86e5d44bb3f87ac143</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7583667$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7583667$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lee, Sin-Woo</creatorcontrib><creatorcontrib>Do, Hyun-Lark</creatorcontrib><title>Zero-Ripple Input-Current High-Step-Up Boost–SEPIC DC–DC Converter With Reduced Switch-Voltage Stress</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description>This paper proposes a zero-ripple input-current high-step-up boost-single ended primary inductor converter (SEPIC) dc-dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost-SEPIC dc-dc converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low R ds(on) , can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype.</description><subject>Capacitors</subject><subject>Cascaded boost–single ended primary inductor converter (SEPIC) converter</subject><subject>Circuits</subject><subject>Clamping circuits</subject><subject>Clamps</subject><subject>Converters</subject><subject>DC-DC power converters</subject><subject>Electric potential</subject><subject>Energy conversion efficiency</subject><subject>high-step-up converter</subject><subject>Inductors</subject><subject>MOSFETs</subject><subject>Power efficiency</subject><subject>ripple-free technic</subject><subject>Stress</subject><subject>Switches</subject><subject>Switching circuits</subject><subject>Voltage converters (DC to DC)</subject><subject>Voltage gain</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kNtKw0AQhhdRsFYfQLxZ8Hrrzh5yuNRYbaFgaVoFb0IOkzalNnF3o3jnO_iGPokpLV7NMHz_P_ARcgl8AMDDm_l0OBkIDt5AeKAll0ekB6ECxoH7x6THg0CzIAzlKTmzds05KM2hR6pXNDWbVU2zQTreNq1jUWsMbh0dVcsVix02bNHQu7q27vf7Jx5OxxG9j7r1PqJRvf1A49DQl8qt6AyLNseCxp-Vy1fsud64dIk0dgatPScnZbqxeHGYfbJ4GM6jEZs8PY6j2wnLRSgdgzRHqQtPicALschKpVMRlqhzFWgvzHShVJlzqSCTQpSBh7tLlsky8NMclOyT631vY-r3Fq1L1nVrtt3LRICvlBagg46CPZWb2lqDZdKY6i01XwnwZGc02RlNdkaTg9Euc7XPVIj4z_tdm-f58g8Vm3MN</recordid><startdate>201708</startdate><enddate>201708</enddate><creator>Lee, Sin-Woo</creator><creator>Do, Hyun-Lark</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope></search><sort><creationdate>201708</creationdate><title>Zero-Ripple Input-Current High-Step-Up Boost–SEPIC DC–DC Converter With Reduced Switch-Voltage Stress</title><author>Lee, Sin-Woo ; Do, Hyun-Lark</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-1ace35d642869edbf45a29fe5c48569b5d44fc0341b322f86e5d44bb3f87ac143</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Capacitors</topic><topic>Cascaded boost–single ended primary inductor converter (SEPIC) converter</topic><topic>Circuits</topic><topic>Clamping circuits</topic><topic>Clamps</topic><topic>Converters</topic><topic>DC-DC power converters</topic><topic>Electric potential</topic><topic>Energy conversion efficiency</topic><topic>high-step-up converter</topic><topic>Inductors</topic><topic>MOSFETs</topic><topic>Power efficiency</topic><topic>ripple-free technic</topic><topic>Stress</topic><topic>Switches</topic><topic>Switching circuits</topic><topic>Voltage converters (DC to DC)</topic><topic>Voltage gain</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lee, Sin-Woo</creatorcontrib><creatorcontrib>Do, Hyun-Lark</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Sin-Woo</au><au>Do, Hyun-Lark</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Zero-Ripple Input-Current High-Step-Up Boost–SEPIC DC–DC Converter With Reduced Switch-Voltage Stress</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2017-08</date><risdate>2017</risdate><volume>32</volume><issue>8</issue><spage>6170</spage><epage>6177</epage><pages>6170-6177</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract>This paper proposes a zero-ripple input-current high-step-up boost-single ended primary inductor converter (SEPIC) dc-dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost-SEPIC dc-dc converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low R ds(on) , can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2016.2615303</doi><tpages>8</tpages></addata></record> |
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| issn | 0885-8993 1941-0107 |
| language | eng |
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| subjects | Capacitors Cascaded boost–single ended primary inductor converter (SEPIC) converter Circuits Clamping circuits Clamps Converters DC-DC power converters Electric potential Energy conversion efficiency high-step-up converter Inductors MOSFETs Power efficiency ripple-free technic Stress Switches Switching circuits Voltage converters (DC to DC) Voltage gain |
| title | Zero-Ripple Input-Current High-Step-Up Boost–SEPIC DC–DC Converter With Reduced Switch-Voltage Stress |
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