Zero-Ripple Input-Current High-Step-Up Boost–SEPIC DC–DC Converter With Reduced Switch-Voltage Stress

This paper proposes a zero-ripple input-current high-step-up boost-single ended primary inductor converter (SEPIC) dc-dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost-SEPIC dc-dc converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low R ds(on) , can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype.