Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM

This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. The proposed architecture does not require fine-grained fault location, and the error map is stored in non-volatile resistive memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the FPGA. The power gating scheme is implemented to save idle leakage power and fix hardware faults in the power network. Significant yield enhancement is expected using this architecture. The architecture has been verified in a test chip fabricated in 28nm technology. Redundancy operation is solely controlled by on chip fault locators which are HfO 2 -based resistive memories monolithically integrated after CMOS process. The maximum shift in performance is about 2 percent when the redundancy is engaged, and the power footprint is unaffected.