Up-Conversion of Clock Phase Noise in Plesiochronous Data Links

A great number of recent standards for high-speed data-links permit a small difference, usually measured in parts-per-millions, between transmitter and receiver clock frequencies. Technically known as plesiochronous systems, this small difference in frequency forces the receiver clock and data recovery circuit (CDR) to continuously "rotate" the phase interpolator code to maintain the recovered clock edges always aligned with the incoming data. However, the "rotation" of the phase interpolator causes the phase noise, deterministic and random, of the receiver local clock to be up-converted in frequency. As a result, phase noise components that are normally assumed to be filtered out by the CDR can, in reality, reappear through their up-converted images well above the CDR bandwidth and thus significantly degrades the recovered clock jitter performance. After an intuitive description, this brief provides a mathematical model of the phenomenon and shows how the effect is different based on whether the up-converted phase noise is correlated or un-correlated among the several local clock phases that are used to reconstruct the recovered clock. A standard 10 Gb/s serial link with frequency offset between transmitter and receiver is, then, used as a practical example to describe this phenomenon. The total additional jitter that must be expected at the recovered clock is reported as a function of the frequency offset.