A New Method for Design of CNFET-Based Quaternary Circuits

In this paper, a new method for designing quaternary circuits in carbon nanotube field-effect transistor (CNFET) technology is proposed. Beyond many advantages of multi-valued logics (MVLs), the conversion of bits of a byte between quaternary and binary logic is easy and can be done independently. Therefore, this logic can be used effectively for wholly quaternary circuit design or beside binary logic as part of a great digital system. Thanks to particular capabilities of CNFET technology, proposed designs are implemented in this technology. These complementary symmetric gates are merely made by transistors and require only one supply voltage in addition to ground level. The proposed design for implementing standard quaternary inverter (SQI) generates three inherently binary inverters in quaternary logic as well: positive quaternary inverter (PQI), negative quaternary inverter (NQI) and symmetric quaternary inverter (SyQI). Based on the proposed design, new quaternary NAND (QNAND) and quaternary NOR (QNOR) gates are presented as well. These gates could be used as fundamental blocks for implementing complex digital circuits. QNAND and QNOR may be designed to adopt up to four inputs; however, in general applications, designs with two inputs are used. Proposed gates are simulated by means of Synopsys HSPICE tool with the standard 32 nm CNFET Stanford model, and performance parameters including maximum delay time, average power and energy consumption are extracted and compared with the simulation results of the state-of-the-art designs. The results indicate priority of proposed designs such that the delay time and energy consumption are roughly equal or less than half and one-third of other presented designs, respectively. Moreover, the voltage transfer curve (VTC) of proposed gates demonstrates the proper noise margin values from 90 mV up to 113 mV for different gates. For evaluating stability and robustness of these gates, more simulations are carried out by considering process deviations in which the proposed designs demonstrate proper performance among all in the most simulations.