Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths

Vertical gate-all-around (GAA) junctionless nanowire transistors (JNTs) with different diameters and underlap lengths are investigated using three-dimensional device simulations. The source-side diameter determines the on-current and drain-induced barrier lowering characteristics, whereas the drain-side diameter controls the band-to-band tunneling current during off-state conditions. The JNTs with short drain-side underlap lengths decrease the source/drain series resistance but increase the off-current values, especially due to large band-gap narrowing effects at the drain extension region. Proper device design of vertical GAA JNTs considering the device structure and underlap is needed to improve both on/off and short channel characteristics.