Concurrent multi-mode timing model generation for hierarchical timing analysis

In this paper, we investigate the challenges in timing model generation for designs operating at various functional modes and timing corners for reducing the overall complexity of timing verification besides preserving the key intent of IP protection. We also propose a method for concurrently generating a model that can address the requirements of timing verification of a set of functional constraint modes belonging to the same corner with a given process, voltage and temperature specifications. Eventually we present a comparison of this proposed technique to the standard timing model generation technique and outline the advantages in three metrics of accuracy, performance and compaction of the timing models.