A New Power Gating Circuit Design Approach Using Double-Gate FDSOI

Power gating circuits are utilized to manage power consumption and thermal stress in microprocessors and other high-performance integrated circuits. Most of the power gating techniques utilize sleep transistors in different configurations to reduce the subthreshold leakage current, which is the primary source of the standby power. These sleep transistors, which are added between the supply lines and the circuits as header and footer switches, impose additional area, delay, power, and other overheads and complexities. This brief introduces the concept of combining the functionality of the sleep transistors with the logic devices by utilizing fully depleted silicon-on-insulator (FDSOI) device. This FDSOI transistor-based power gating circuit design approach will eliminate the requirement of employing a separate set of sleep transistors to place the circuit in the sleep or idle mode. This will reduce the overall complexity and overheads of integrated circuits and simplify power gating techniques. In addition, it improves the overall power efficiency and lower thermal effects. SOI devices are becoming critically important for various very-large-scale integration applications, because SOI devices provide higher performance and reliability, and options to design circuits with multiple-threshold voltages to ensure faster switching and lower power consumption. In the proposed circuit design approach, the flexibility to control the threshold voltage of a double-gate FDSOI device via back gate has been exploited to eliminate the need for using a separate set of sleep transistors. The presented sleep transistor design is verified via HSPICE simulation using the Leti-UTSOI model from CEA-Leti.