Design of a Hybrid Controller ASIC for a VRM Using a 90-nm CMOS Process

This paper proposes an application-specified integrated circuit implementation of the nonlinear controller in voltage regulator modules for high-end microprocessors first proposed by Mazumder and demonstrated on discrete level by Mazumder and Kamisetty. The design scheme is presented where the driver is separated from the controller to enable its integration with the MOSFET using the Driver-MOSFET concept proposed by Intel ( DrMOS Technical Specifications , Revision 1.0, Nov. 2004). The controller, which is designed using the ST's 90-nm CMOS process, has increased speed and size performance and can be integrated into the I/O hub or Southbridge component PC chipsets, which are similarly fabricated on submicrometer processes. The transconductance of the process is, however, low giving rise to accuracy problems. We validated the design in simulations by comparing system and transistor-level implementation in Saber and Cadence, respectively. The nonlinear control scheme coupled with adaptive voltage positioning (AVP) enables high-speed response to load transients at relatively constant output impedance. The design is realized in layout with Calibre's verification tool running ST's design rule check runset and is layout versus schematic clean.