Compensation method of phase‐locked loop under unbalanced grid condition based on harmonic linearization

Summary The voltage source converter (VSC) is often faced with unbalanced grid conditions that will degrade its performance because of the distorted current with a large amount of harmonics. One of the main parts of current distortion is the third‐order harmonics caused by the negative‐sequence voltage component at the fundamental frequency. The distorted output of the synchronous reference frame phase‐locked loop (SRF‐PLL) due to the unbalanced grid voltage is the main reason for the existence of the harmonics. This paper analyzes the mechanism of the generation of harmonics currents and proposes a compensation method for the PLL in VSCs based on the harmonic linearization method without changing the structure of SRF‐PLL. The proposed PLL can work properly under unbalanced grid conditions and has a good dynamic response. The third‐order current harmonics are reduced significantly by using the proposed PLL instead of the conventional SRF‐PLL without changing the current control strategy of VSC. The compensation method is verified by cycle‐by‐cycle circuit simulations and controller hardware‐in‐the‐loop experiments. This paper analyzes the mechanism of the harmonics current and proposes a compensation method for the PLL used in VSCs using harmonic linearization without changing the structure of SRF‐PLL. The proposed PLL can work properly under unbalance grid condition and has a good dynamic response. The THD of the third‐order harmonics current is decreased significantly by using the proposed PLL instead of the SRF‐PLL without changing the current control strategy of VSC.