Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks
For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important find...
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| Veröffentlicht in: | IPSJ Transactions on System LSI Design Methodology 2013, Vol.6, pp.122-126 |
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| container_title | IPSJ Transactions on System LSI Design Methodology |
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| creator | Hara-Azumi, Yuko Matsuba, Toshinobu Tomiyama, Hiroyuki Honda, Shinya Takada, Hiroaki |
| description | For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary to conventional wisdom or have not been sufficiently handled. These five findings will be useful for the further development and advance of the practical HLS technology. |
| doi_str_mv | 10.2197/ipsjtsldm.6.122 |
| format | Article |
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| ispartof | IPSJ Transactions on System LSI Design Methodology, 2013, Vol.6, pp.122-126 |
| issn | 1882-6687 1882-6687 |
| language | eng |
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| source | J-STAGE Free; Freely Accessible Japanese Titles; Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals |
| subjects | Benchmarks High level synthesis Level (quantity) multiplexer Quantitative analysis resource sharing |
| title | Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks |
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