A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display

A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display

A 10 Gbps transmitter bridge chip including four data lanes, which increases the bandwidth using an 8-to-1 serialization, is proposed for a field-programmable gate array (FPGA)-based frame generator to support the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) d...

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Veröffentlicht in:IEICE Transactions on Electronics 2017/11/01, Vol.E100.C(11), pp.1035-1038
Hauptverfasser: KIM, Ho-Seong, LEE, Pil-Ho, HAN, Jin-Wook, SHIN, Seung-Hun, BAEK, Seung-Wuk, PARK, Doo-Ill, SEO, Yongkyu, JANG, Young-Chan
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Sprache:eng
Schlagworte:
DSI
Field programmable gate arrays
FPGA-based frame generator
Microprocessors
MIPI D-PHY
Paths
phase-locked loop
transmitter bridge chip
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container_end_page 1038
container_issue 11
container_start_page 1035
container_title IEICE Transactions on Electronics
container_volume E100.C
creator KIM, Ho-Seong
LEE, Pil-Ho
HAN, Jin-Wook
SHIN, Seung-Hun
BAEK, Seung-Wuk
PARK, Doo-Ill
SEO, Yongkyu
JANG, Young-Chan
description A 10 Gbps transmitter bridge chip including four data lanes, which increases the bandwidth using an 8-to-1 serialization, is proposed for a field-programmable gate array (FPGA)-based frame generator to support the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) display serial interface (DSI).
doi_str_mv 10.1587/transele.E100.C.1035
format Article
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source J-STAGE
subjects DSI
Field programmable gate arrays
FPGA-based frame generator
Microprocessors
MIPI D-PHY
Paths
phase-locked loop
transmitter bridge chip
title A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display
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