Design and Implementation of a Flexible Multi-Mode DVB-T/H Receiver and Extension to DVBT-2

The implementation of broadcasting receiver requires intensive computation of signal processing algorithms, which makes it support up to 50 Mbit/s data transmission. Furthermore, many different operational modes defined in DVB-X standards inevitably require more chip area when implemented in hardware, and substantially increases the design cost when supporting multiple broadcasting standards. Uses of reconfigurable hardware can leads to fast execution and reduces power consumption while maintaining flexibility. These architectures are now suitable for supporting complex and computationally intensive applications. This work presents a flexible DVB-T/H multi-mode demodulator. The major computation requirements of DVB-T/H standard system are identified. The DVB-T/H multi-mode receiver is implemented in real time on the dynamic coarse grained reconfigurable architecture (DART) running at 200 MHz. This implementation permits a dynamic switch from a mode to another. This multi-mode receiver can then accommodate a reliability/energy efficiency trade-off. It’s demonstrated that DART has an overall consumption of 279.4 mW for the most computational mode of DVB-T/H. By applying the adaptation of inner code rate, change of modulation, power slicing optimizations up to 67 % of power reduction can be achieved. This paper discusses the feasibility of extending DVB-T/H demodulator implementation on DART cluster to support DVB-T2 standard features.