A DC Model of the Planar Dual‐Gated FD‐SOI MOSFET that Captures the Effects of High Biases and HALO

No models exist for fully depleted silicon‐on‐insulator (FD‐SOI) metal‐oxide‐silicon field‐effect‐transistors (MOSFETs) that operate at high currents and voltages. Operation at high currents and voltages dictates the radio‐frequency (rf) output power that such devices can deliver and transmit from the particular rf‐integrated circuits used in today's cellular phones. In this work, a first order dc model for FD‐SOI MOSFETs that are specifically designated to operate at high biases and large rf swings is presented. These devices typically incorporate HALO and body‐tied‐source (BTS), which enable much higher biases to be applied to the gate and drain and allow larger rf swings. They also employ dual‐gated designs that further reduce the threshold voltage and increase the current. Although the newly established model accurately replicates the general dc behavior of any FD‐SOI MOSFET that incorporates HALO and BTS, it is specifically tailored to an innovative and recently patented device structure for FD‐SOI MOSFET. The new structure adopts an improved and unique design for BTS and HALO that most effectively filters the impact‐ionization current to BTS and improves the device performance. New design rules that enable the designs of area‐efficient layouts for FD‐SOI MOSFETs that incorporate the HALO and BTS are also presented. In this work, an accurate and simple dc model for a fully depleted silicon‐on‐insulator (FD‐SOI) metal‐oxide‐silicon field‐effect‐transistor (MOSFET) that incorporates HALO and body‐tied‐sourc (BTS) is demonstrated for the very first time. The influence from the built‐in parasitic bipolar structure at high currents and voltages is very accurately captured. The model is also used to accurately calculate the subthreshold current, the SS, and the VTSC.