Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

In this paper, we present the fabrication method of asymmetric independent dual-gate FinFETs with different gate stack using sidewall spacer patterning and two-step chemical-mechanical polishing (CMP) processes. The fin width is controlled as a result of sidewall spacer patterning. The two-step CMP processes are conducted to separate two gates and to make different gate stacks for each gate, respectively. The fabricated devices can be used for multiple applications by utilizing independent two gates. First of all, the independent two gates offer the flexible threshold voltage modulation properties by applying the second gate (G2) bias with little subthreshold swing degradation. Second, the device can be utilized as a charge trap flash memory cell by trapping electrons in the charge storage layer. These results provide a possible way to fabricate asymmetric independent dual-gate FinFETs having potential as a multi-functional single device. [Display omitted] •The fabrication method of asymmetric independent dual-gate FinFET with different gate stack is proposed.•The fin width is controlled by modulating the thickness of sidewall spacer, and two gates are separated by CMP processes.•The fabricated device can be used for multiple applications including flexible VT modulation and non-volatile memory function.