An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications

This paper presents an asynchronous-clocking successive approximation register (SAR) analog-to-digital converter (ADC) suitable for ultralow-power fine-precision sensor applications whose signal bandwidth is in the kilohertz range. The performance-limiting issues of comparator noise and capacitor mi...

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Veröffentlicht in:IEEE journal of solid-state circuits 2018-02, Vol.53 (2), p.404-417
Hauptverfasser: Choi, Seungnam, Ku, Hwan-Seok, Son, Hyunwoo, Kim, Byungsub, Park, Hong-June, Sim, Jae-Yoon
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Sprache:eng
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Zusammenfassung:This paper presents an asynchronous-clocking successive approximation register (SAR) analog-to-digital converter (ADC) suitable for ultralow-power fine-precision sensor applications whose signal bandwidth is in the kilohertz range. The performance-limiting issues of comparator noise and capacitor mismatch in SAR ADC are resolved by a residue integration scheme combined with a dynamic element matching (DEM), achieving a high resolution without imposing extra burden on the design of residue amplifier and comparator. The prototype 16-bit 2 kS/s SAR ADC is fabricated using 180-nm CMOS process in an area of 0.68 mm 2 . Measurements show 84.6-dB signal to noise and distortion ratio and 98.2-dB spurious-free dynamic range at the Nyquist input frequency. The ADC dissipates 7.93 μW from supply voltage of 1.8 V and achieves a Schreier figure of merit of 165.6 dB.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2017.2774287