A 0.18- \mu \text CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1}^} Noise at 3.8- \mu \text Conversion Time

A CMOS image sensor (CIS) is presented, simultaneously achieving low noise and high frame rate. The imager innovatively employs column-parallel dual-slope (DS) integrating analog-to-digital converters (ADCs) based on a phase-delay-counting principle and using oversampling to suppress the readout thermal noise. A noise analysis of the DS-integrating ADC in correlated-double-sampling operation is provided to prove the low-noise advantage of the proposed architecture. Furthermore, the design considerations of the presented architecture are derived based on the analysis of nonideality effects. Based on these analytical results, design tradeoffs are discussed and applied in the test chip. The test chip, fabricated in a 4M1P 0.18-μm CIS technology, contains a 128 × 128 pixel array. The measurement results show that each of the 128 column-level ADCs converts a pixel in 3.8 μs and achieves a noise floor of 1e rms - . The chip consumes 49 mW excluding the I/O power and 59 mW including the I/O power, resulting in a very good figure of merit value of 1.4 and 1.7 [e - .nJ], respectively.