Impacts of Diameter and Ge Content Variation on the Performance of Si1-xGex p-Channel Gate-All-Around Nanowire Transistors
In this work, the impacts of both nanowire diameter (D NW ) and Ge content (%) on the performance of Si 1−x Ge x Gate-all-around nanowire p -channel FETs are investigated. The variations in SiGe Gate-all-around nanowire p -channel FETs induced by D NW variation, Ge content variation, and some stocha...
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Veröffentlicht in: | IEEE transactions on nanotechnology 2018-01, Vol.17 (1), p.108-112 |
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creator | Zhang, Xianle Liu, Xiaoyan Yin, Longxiang Du, Gang |
description | In this work, the impacts of both nanowire diameter (D NW ) and Ge content (%) on the performance of Si 1−x Ge x Gate-all-around nanowire p -channel FETs are investigated. The variations in SiGe Gate-all-around nanowire p -channel FETs induced by D NW variation, Ge content variation, and some stochastic process variations including random dopants fluctuation, gate edge roughness, and metal gate granularity are also evaluated. |
doi_str_mv | 10.1109/TNANO.2017.2774244 |
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The variations in SiGe Gate-all-around nanowire p -channel FETs induced by D NW variation, Ge content variation, and some stochastic process variations including random dopants fluctuation, gate edge roughness, and metal gate granularity are also evaluated.</description><identifier>ISSN: 1536-125X</identifier><identifier>EISSN: 1941-0085</identifier><identifier>DOI: 10.1109/TNANO.2017.2774244</identifier><identifier>CODEN: ITNECU</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject><![CDATA[D<named-content xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" content-type="math" xlink:type="simple"> <inline-formula> <tex-math notation="LaTeX"> {_\text{NW}}</tex-math> </inline-formula> </named-content> variation ; Field effect transistors ; Fluctuations ; Gallium arsenide ; gate-all-around nanowire p-channel FETs ; Ge content ; Ions ; Logic gates ; Nanowire diameter ; Nanowires ; Resource description framework ; Semiconductor devices ; Silicon germanides ; Silicon germanium ; stochastic process variations ; TCAD simulation ; Transistors ; Variation]]></subject><ispartof>IEEE transactions on nanotechnology, 2018-01, Vol.17 (1), p.108-112</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The variations in SiGe Gate-all-around nanowire p -channel FETs induced by D NW variation, Ge content variation, and some stochastic process variations including random dopants fluctuation, gate edge roughness, and metal gate granularity are also evaluated.</description><subject><![CDATA[D<named-content xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" content-type="math" xlink:type="simple"> <inline-formula> <tex-math notation="LaTeX"> {_\text{NW}}</tex-math> </inline-formula> </named-content> variation]]></subject><subject>Field effect transistors</subject><subject>Fluctuations</subject><subject>Gallium arsenide</subject><subject>gate-all-around nanowire p-channel FETs</subject><subject>Ge content</subject><subject>Ions</subject><subject>Logic gates</subject><subject>Nanowire diameter</subject><subject>Nanowires</subject><subject>Resource description framework</subject><subject>Semiconductor devices</subject><subject>Silicon germanides</subject><subject>Silicon germanium</subject><subject>stochastic process variations</subject><subject>TCAD simulation</subject><subject>Transistors</subject><subject>Variation</subject><issn>1536-125X</issn><issn>1941-0085</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kN9LwzAQx4soOKf_gL4EfM7MjyZNH8fUOhib4BTfStpeWaVNZpLh9K-3dUM4uHv4fu64TxRdUzKhlKR36-V0uZowQpMJS5KYxfFJNKJpTDEhSpz2s-ASUybez6ML7z9In5RCjaKfebfVZfDI1ui-0R0EcEibCmWAZtYEMAG9adfo0FiD-gobQM_gaus6bUoYuJeG4n0Ge7TFs402BlqU6QB42rZ46uyu37bUxn41DtDaaeMbH6zzl9FZrVsPV8c-jl4fH9azJ7xYZfPZdIFLloqApShS4EVRSikYKVVRCMa04rWoy5jLilacxzWQQiap0ISISg-vSZKoWBHN-Di6PezdOvu5Ax_yD7tzpj-Z01TJmCkhSJ9ih1TprPcO6nzrmk6775ySfHCc_znOB8f50XEP3RygBgD-AUUpF5LxXzOXd8U</recordid><startdate>201801</startdate><enddate>201801</enddate><creator>Zhang, Xianle</creator><creator>Liu, Xiaoyan</creator><creator>Yin, Longxiang</creator><creator>Du, Gang</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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title | Impacts of Diameter and Ge Content Variation on the Performance of Si1-xGex p-Channel Gate-All-Around Nanowire Transistors |
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