Improving the operational voltage of vertical organic field effect transistor (VOFET) by altering the morphology of dielectric layer

This work aims at improving the performance of vertical organic field effect transistor (VOFET) by synthesizing the different morphology of dielectric layer; porous and non-porous to be used in the fabrication of 3-dimensional (3D) VOFET. In this work, poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] 75/25 have been used as a dielectric layer in the fabrication of 3D VOFET. To produce the 3D VOFET, porous alumina template is applied as to allow the replicating process between the template and P(VDF-TrFE) to occur. It is found that the replicating process has generated the porous structure of P(VDF-TrFE). Two types of VOFET, one with the integration of porous and one without the porous have been fabricated and characterized. VOFET without the porous has the current of 3.5 × 10 −4 A obtained at drain-source voltage (V DS ) of 25 V with the turn-on voltage of 10 V. Meanwhile, the VOFET integrated with porous recorded a better current of 2.0 × 10 −3 A at V DS of 25 V with the turn-on voltage of 7 V.