Reverse Converters for the Moduli Set {2n,2n-1-1,2n-1,2n+1-1}(nEven)
In this paper, two residue number system (RNS) to binary converters for the moduli set { 2 n , 2 n - 1 - 1 , 2 n - 1 , 2 n + 1 - 1 } for ( n even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decod...
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creator | Ananda Mohan, P. V. |
description | In this paper, two residue number system (RNS) to binary converters for the moduli set {
2
n
,
2
n
-
1
-
1
,
2
n
-
1
,
2
n
+
1
-
1
}
for (
n
even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (
A
), conversion time (
T
),
AT
and
A
T
2
trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the
(
2
n
+
1
)
channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented. |
doi_str_mv | 10.1007/s00034-017-0725-0 |
format | Article |
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2
n
,
2
n
-
1
-
1
,
2
n
-
1
,
2
n
+
1
-
1
}
for (
n
even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (
A
), conversion time (
T
),
AT
and
A
T
2
trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the
(
2
n
+
1
)
channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented.</description><identifier>ISSN: 0278-081X</identifier><identifier>EISSN: 1531-5878</identifier><identifier>DOI: 10.1007/s00034-017-0725-0</identifier><language>eng</language><publisher>New York: Springer US</publisher><subject>Circuits and Systems ; Conversion ; Converters ; Electrical Engineering ; Electronics and Microelectronics ; Engineering ; Hardware ; Instrumentation ; Preferred stock ; Residue number systems ; Signal,Image and Speech Processing</subject><ispartof>Circuits, systems, and signal processing, 2018-08, Vol.37 (8), p.3605-3634</ispartof><rights>Springer Science+Business Media, LLC, part of Springer Nature 2017</rights><rights>Circuits, Systems, and Signal Processing is a copyright of Springer, (2017). All Rights Reserved.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s00034-017-0725-0$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s00034-017-0725-0$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,780,784,27922,27923,41486,42555,51317</link.rule.ids></links><search><creatorcontrib>Ananda Mohan, P. V.</creatorcontrib><title>Reverse Converters for the Moduli Set {2n,2n-1-1,2n-1,2n+1-1}(nEven)</title><title>Circuits, systems, and signal processing</title><addtitle>Circuits Syst Signal Process</addtitle><description>In this paper, two residue number system (RNS) to binary converters for the moduli set {
2
n
,
2
n
-
1
-
1
,
2
n
-
1
,
2
n
+
1
-
1
}
for (
n
even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (
A
), conversion time (
T
),
AT
and
A
T
2
trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the
(
2
n
+
1
)
channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented.</description><subject>Circuits and Systems</subject><subject>Conversion</subject><subject>Converters</subject><subject>Electrical Engineering</subject><subject>Electronics and Microelectronics</subject><subject>Engineering</subject><subject>Hardware</subject><subject>Instrumentation</subject><subject>Preferred stock</subject><subject>Residue number systems</subject><subject>Signal,Image and Speech Processing</subject><issn>0278-081X</issn><issn>1531-5878</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNpNkE1LxDAQhoMoWFd_gLeCF0Wjk0nTJEep6wesCH6At7Cmie6ypLVp9yL-d7PWgwzM-xxeZuAh5JDBOQOQFxEAeEGBSQoSBYUtkjHBGRVKqm2SAUpFQbHXXbIX4xKA6UJjRq4e3dp10eVVExL0iXPfdHn_4fL7ph5Wi_zJ9fkXhjMMlFH2G2mdJv4-DtO1Cyf7ZMfPV9Ed_OWEvFxPn6tbOnu4uasuZ7RFLHuq8M0LzXVZepGmlLpGi-BRubmutQVVF55bJXihtSzRl94KAcxzZq3VyCfkaLzbds3n4GJvls3QhfTSMC1RSdQSUgvHVmy7RXh33b8WmI0tM9oyyZbZ2DLAfwBjTVkA</recordid><startdate>20180801</startdate><enddate>20180801</enddate><creator>Ananda Mohan, P. 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V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p226t-82bf593966f5f5f679d2c20f28ea9d9c08d4f3c853499762f6fc5501f31ccc923</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Circuits and Systems</topic><topic>Conversion</topic><topic>Converters</topic><topic>Electrical Engineering</topic><topic>Electronics and Microelectronics</topic><topic>Engineering</topic><topic>Hardware</topic><topic>Instrumentation</topic><topic>Preferred stock</topic><topic>Residue number systems</topic><topic>Signal,Image and Speech Processing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ananda Mohan, P. V.</creatorcontrib><collection>ProQuest Central (Corporate)</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>Science Database (Alumni Edition)</collection><collection>Computing Database (Alumni Edition)</collection><collection>ProQuest Pharma Collection</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>ProQuest Engineering Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Computing Database</collection><collection>Science Database</collection><collection>Engineering Database</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><collection>ProQuest Central Basic</collection><collection>DELNET Engineering & Technology Collection</collection><jtitle>Circuits, systems, and signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ananda Mohan, P. V.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Reverse Converters for the Moduli Set {2n,2n-1-1,2n-1,2n+1-1}(nEven)</atitle><jtitle>Circuits, systems, and signal processing</jtitle><stitle>Circuits Syst Signal Process</stitle><date>2018-08-01</date><risdate>2018</risdate><volume>37</volume><issue>8</issue><spage>3605</spage><epage>3634</epage><pages>3605-3634</pages><issn>0278-081X</issn><eissn>1531-5878</eissn><abstract>In this paper, two residue number system (RNS) to binary converters for the moduli set {
2
n
,
2
n
-
1
-
1
,
2
n
-
1
,
2
n
+
1
-
1
}
for (
n
even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (
A
), conversion time (
T
),
AT
and
A
T
2
trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the
(
2
n
+
1
)
channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented.</abstract><cop>New York</cop><pub>Springer US</pub><doi>10.1007/s00034-017-0725-0</doi><tpages>30</tpages></addata></record> |
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language | eng |
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source | SpringerLink Journals - AutoHoldings |
subjects | Circuits and Systems Conversion Converters Electrical Engineering Electronics and Microelectronics Engineering Hardware Instrumentation Preferred stock Residue number systems Signal,Image and Speech Processing |
title | Reverse Converters for the Moduli Set {2n,2n-1-1,2n-1,2n+1-1}(nEven) |
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