Reverse Converters for the Moduli Set {2n,2n-1-1,2n-1,2n+1-1}(nEven)
In this paper, two residue number system (RNS) to binary converters for the moduli set { 2 n , 2 n - 1 - 1 , 2 n - 1 , 2 n + 1 - 1 } for ( n even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decod...
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Veröffentlicht in: | Circuits, systems, and signal processing systems, and signal processing, 2018-08, Vol.37 (8), p.3605-3634 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | In this paper, two residue number system (RNS) to binary converters for the moduli set {
2
n
,
2
n
-
1
-
1
,
2
n
-
1
,
2
n
+
1
-
1
}
for (
n
even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (
A
), conversion time (
T
),
AT
and
A
T
2
trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the
(
2
n
+
1
)
channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented. |
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ISSN: | 0278-081X 1531-5878 |
DOI: | 10.1007/s00034-017-0725-0 |