Parity driven reconfigurable duplex system

This paper proposes a method improving the fault-coverage capabilities of (FPGA) designs. Faults are mostly (SEUs) in the configuration memory of SRAM-based (FPGA) and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection techniques and the basic architectures of actual modern (FPGA) – the Look-Up Table (LUT) with two outputs. The main part of the paper is the description of the proposed method (PWtf) based on a cascade – waterfall – of several waves of inner parity generating the final parity of outputs of the whole circuit. The proposed PWtf method utilizes the (mostly) unused output of a two-output LUT to cover any single possible routing or LUT fault with a small area overhead. The encapsulation of the proposed PWtf method into a Duplication with Comparison scheme is presented in the second part of the paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method and a similar existing technique – Duplication with Comparison (DwC), and between the encapsulated PWtf method and TMR. The proposed method has a lower relative overhead and requires a lower number of inputs and outputs.